In integrated circuit design, a Register Transfer Level (RTL) description is a way of describing the operation of a synchronous digital circuit at a low level that essentially matches the gate level components making up the electronic component in the integrated circuit and is synthesizable to produce a hardware representation of that RTL description. In RTL design, a circuit's behavior is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals. Register transfer level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level gate representations and ultimately actual wiring can be derived. SystemC is often thought of as a hardware description language like VHDL and Verilog, but is more aptly described as a system description software programming language, since it exhibits its real power during transaction-level modeling and behavioral modeling.
Transaction-level modeling (TLM) is a high-level approach to modeling digital systems where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. A transaction-level model can be a software-coded model of a circuit or a system where data transfers are simplified and abstracted. Transaction Layer 1 modeling refers to a level of detail where the data is passed in packet structures and the protocol is modeled accurately during active transfer phases only. Transaction Level is simply a level where individual signals are represented in the software-coded model in a way that can be mapped directly to corresponding signals in a RTL description.